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[VHDL-FPGA-Verilog] Design_of_Programmable_Music_Generator

Description: 根据音乐发生的机理，将复杂可编程逻辑器件作为发生音乐的核心器件，用高速集成电路硬件描述语言编程描述发生的音乐乐谱，配合周边硬件电路，由电声转换发声器接收信号，从而发出音乐声，实验表明，采用该方法设计的音乐发生器成本低、修改方便-Music took place in accordance with the mechanism of complex programmable logic device, as occurred in the core of music devices, with high-speed integrated circuit hardware description language to describe the occurrence of music notation, with the peripheral hardware circuits, electro-acoustic conversion by the audible signal device to receive signals, which issued music, experiments show that this method of music generator design and low cost, easy to amend
Platform: | Size: 193536 | Author: shenshunan | Hits:

[Embeded-SCM Develop] spiinterfaceverilog

Description: SPI Master Core Specification，This document provides specifications for the SPI (Serial Peripheral Interface) Master core-SPI Master Core Specification, This document provides specifications for the SPI (Serial Peripheral Interface) Master core
Platform: | Size: 82944 | Author: 贾远鸿 | Hits:

[VHDL-FPGA-Verilog] 00011ipcore51

Description: 51内核单片机的VHDL语言的实现,从功能到编译都有详细说明,包括源码-51-core single-chip realization of the VHDL language, from the function to compile a detailed description, including source
Platform: | Size: 739328 | Author: 林风 | Hits:

[VHDL-FPGA-Verilog] Viterbi_IP

Description: viterbi译码器的IP核，可以直接编译使用-viterbi decoder IP core, the compiler can directly use
Platform: | Size: 75776 | Author: nianln | Hits:

[VHDL-FPGA-Verilog] FPGAdezizhixingSPWMboChengXu

Description: 基于FPGA的自治型SPWM波形发生器的设计！正弦脉宽调制（SPWM）技术在以电压源逆变电路为核心的电力电子装置中有着广泛的应用，如何产生SPWM脉冲序列及其实现手段是PWM技术的关键。大家共同探讨哈！-FPGA based SPWM autonomy-based waveform generator design! Sinusoidal pulse width modulation (SPWM) technology in the voltage source inverter circuit as the core of the power electronic devices have a wide range of applications, how to generate SPWM pulse sequence and its implementation means PWM technology is the key. Kazakhstan investigate everyone!
Platform: | Size: 4096 | Author: 小喻 | Hits:

[VHDL-FPGA-Verilog] 16Point-FFT

Description: 16点FFT VHDL源程序，The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary component of a datum.-16:00 FFT VHDL source code, The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input datais a vector of 16 complex values represented as 16-bit 2 s complement numbers- 16-bits foreach of the real and imaginary component of a datum.
Platform: | Size: 1824768 | Author: qiyuan | Hits:

[CA auth] sha1_v01

Description: SHA-1加密算法的IP核，内涵文档，仿真测试文件-SHA-1 encryption algorithm of the IP core, the connotation of documents, simulation test file
Platform: | Size: 6144 | Author: 徐 | Hits:

[USB develop] usb20_ipcore_usb_funct

Description: usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL description suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
Platform: | Size: 208896 | Author: road | Hits:

[VHDL-FPGA-Verilog] fpga-fpdpsk

Description: FSK/PSK调制顶层文件 ，正弦波模块 ，正弦波模块初始化文件 ，振幅调整及波形选择模块 ，频率显示值地址产生模块 ，频率步进键核心模块 ，弹跳消除电路-FSK/PSK modulation top-level documents, sine-wave modules, module initialization file sine wave, amplitude adjustment and waveform selection module, the frequency of the displayed value address generator module, the frequency of stepping key core modules, bouncing the elimination of circuit
Platform: | Size: 27648 | Author: libing | Hits:

[Software Engineering] fpga_docu

Description: CPLD/FPGA 入门文档。国内某知名fpga开发商编写的基础教程，共18篇。从使用fpga如何点亮led灯到VGA到8051内核使用方法。如果您是打算学习cpld/fpga，建议先阅读这些文章再选择采购开发板。-CPLD/FPGA entry documents. FPGA developers a well-known domestic basis for the preparation of curricula, a total of 18. From how to use the FPGA to the VGA lit lamp led to the 8051 core to use. If you intend to study cpld/fpga, we suggest that you first read the article and then select the procurement development board.
Platform: | Size: 5509120 | Author: gao | Hits:

[VHDL-FPGA-Verilog] 8051core

Description: 8051 VHDL IP Core，有兴趣的可以-8051 VHDL IP Core, who are interested can
Platform: | Size: 25600 | Author: lllixplg | Hits:

[VHDL-FPGA-Verilog] SPI_verilog_vhdl

Description: SPI串口的内核实现（分别使用verilog和vhdl语言描述的）-The core of the realization of SPI serial port (using Verilog and VHDL language description of the)
Platform: | Size: 13312 | Author: 徐剑 | Hits:

[VHDL-FPGA-Verilog] lift_syn

Description: 实现简易4层电梯控制核心模块，完成了电梯上下层控制、指示灯显示、优先级判断等多种常用功能。-The realization of simple 4 layer core elevator control module, the completion of the elevator on the lower control, indicator light shows that determine the priority and many other commonly used functions.
Platform: | Size: 64512 | Author: lixiaoyang | Hits:

[VHDL-FPGA-Verilog] ramvhdllib_06

Description: The Free IP Project VHDL Free-RAM Core-The Free IP ProjectVHDL Free-RAM Core
Platform: | Size: 615424 | Author: cathy | Hits:

[VHDL-FPGA-Verilog] USB

Description: 用VHDL实现的USB IP核，大家可以参考下-Use VHDL to achieve USB IP core, we can refer to the following
Platform: | Size: 1146880 | Author: 蔡飞 | Hits:

[VHDL-FPGA-Verilog] uartvhdl

Description: VHDL语言实现的UART IP核，比较实用-VHDL language to achieve the UART IP core, more practical
Platform: | Size: 412672 | Author: 蔡飞 | Hits:

[VHDL-FPGA-Verilog] PWM

Description: 使用VERILOG 语言产生PWM波。只需要使用处理器或内核直接配置相应的寄存器就可以输出PWM波。-VERILOG language use PWM wave generated. Only need to use the processor or core directly corresponding configuration register can output PWM wave.
Platform: | Size: 2048 | Author: 望习才 | Hits:

[VHDL-FPGA-Verilog] MICO8_DEMO_03_18_08.ZIP

Description: Lattice 超精简8位软核CPU--Mico8，开放所有源代码，包括VHDL，编译器，支持GCC编译器。可在Lattice所有FPGA和MachXO 器件上使用。本例包含示例和说明文档。对使用Lattice器件的用户或者学习CPU设计的人员有较高参考价值。-Lattice super-streamlined eight soft-core CPU- Mico8, open up all the source code, including VHDL, the compiler to support the GCC compiler. Lattice can all FPGA and MachXO devices use. In this case contains examples and documentation. On the use of Lattice devices users or learning CPU design personnel have a higher reference value.
Platform: | Size: 3317760 | Author: ymjcloud | Hits:

[Other] I2C

Description: 详细描述了I2C的技术规范 版本号为2.1 是采用VHDL编写I2C的IP核的一本不错的参考资料-A detailed description of the I2C specification version 2.1 is the use of VHDL for the preparation of the IP core I2C a good reference
Platform: | Size: 283648 | Author: zyq | Hits:

[VHDL-FPGA-Verilog] freerisc8_11

Description: 一个基于VHDL 的简单8位CPU的IP core核心代码-VHDL based on a simple 8-bit CPU core code of the IP core
Platform: | Size: 275456 | Author: wfs | Hits:
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